Euro DesignCon 2005 A Flexible and Adaptive Pipelining Concept for Low Latency Interconnects

This paper describes a semi-hierarchical approach applied to the layout of a challenging multiprocessor ASIC. The ASIC contains several hundred single bit processors on a single chip in a 130 nm technology. The chip is targeted at the massive parallel processing of simple tasks that occur in huge quantities, for example, during hardware emulation. The paper focuses on the complex interconnect network between the processors; the major challenge in the layout of this design. Other interesting details, such as the design style combining hierarchical, flat and custom elements, will also be briefly outlined. Author(s) Biography 1987-1993 studied electrical engineering in Karlsruhe. 1995-1999 research assistant at University of Stuttgart, graduated in 2000 as Ph.D. 1999-2003 physical design engineer, IBM Entwicklung GmbH/Germany. Since 2003, methodology lead for IBM world wide ASIC routing solution.